This invention relates to electronic digital logic test methods and apparatus and particularly to those capable of dynamic testing.
Efficient and accurate testing of digital logic systems is an increasingly important consideration for the electronic system designer. An ideal approach is to have test circuits and interfaces built in to the system, to allow initial state loading and prior state restoration, to operate dynamically so testing can occur while the system operates at full speed, and to be transparent to the end application of the system. If the test circuits are truly transparent, normal system operation can continue unaffected by test operation. This allows isolation of faults experienced during system operation which are difficult or impossible to diagnose by more conventional test circuits and/or diagnostic programs.
These design goals are particularly difficult to meet in the context of on-chip testing of very large scale integrated circuits where test circuit layout space and access for external test signals are limited, and switching speeds are critical. In fact, a design philosophy for testability is an absolute must in such situations, such as that typified by the level sensitive scan technique described in U.S. Pat. No. 3,761,695 to Eichelberger, issued Sept. 25, 1973, and assigned to International Business Machines Corporation. However, such techniques enhance testability at the expense of reducing design flexibility.
U.S. Pat. No. 4,357,703 to Van Brunt, issued Nov. 2, 1982, and assigned to Control Data Corporation appears to disclose a system for dynamic logic testing at full clock rates. The system cannot restore a prior state without reloading an input shift register from a test data input, and thus is not transparent to the end application.
U.S. Pat. No. 3,961,254 to Cavaliere, et al., issued June 1, 1976, and assigned to International Business Machines Corporation appears to disclose means for bypassing operational logic circuits to scan information directly into operational registers. The system does not allow testing of operational logic circuits at full speed nor is it capable of testing transparent to the end application.
U.S. Pat. No. 4,566,104 to Bradshaw, et al., issued Jan. 21, 1986, and assigned to International Computers Limited of London, England, appears to disclose a test apparatus including a plurality of series connected bistable elements coupled to combinatorial logic. No mention is made of the need to restore the bistable elements to their pre-test state. Further, because Bradshaw, et al. do not provide means for presetting all bistable elements in the system under test, the diclosed test equipment cannot execute the well-known Roth algorithm for non-functional testing of digital subsystems.